1. Field of the Invention
The present invention relates to DRAMs, and more specifically to DRAMs provided with spare structures for replacement of defective cells.
2. Discussion of the Related Art
FIG. 1A schematically shows a conventional DRAM architecture 2 arranged in rows and columns of memory cells 4 (MC). Each cell 4 (MC) is connected to a bit line 6 and to a word line 8 (WLi), with i ranging from 1 to n, n being the number of memory rows. Each memory cell column includes two bit lines 6 (BL1, BL2). The memory cells of each column are arranged alternately, the cells of the odd and even rows being respectively accessible by first and second bit lines BL1 and BL2. A cell, including a capacitor having a terminal connected to ground and a terminal connected to a bit line via a transistor that can be activated by a word line, is illustrated in FIG. 1B. A row address decoder (not shown) is provided for receiving an address and providing an activation signal on the corresponding word line WLi. A sense amplifier 10 (SA) has its two inputs respectively connected to the two bit lines BL1 and BL2. For clarity, only two bit lines and n rows of memory 2 have been shown in FIG. 1A.
A read/write operation in such a memory includes the following succession of steps. The information to be stored into cells MC is first written into each of these cells. This writing consists, by an addressing of the chosen cell and an appropriate connection of the corresponding bit line, of writing into each cell a high voltage or a low voltage. The low voltage substantially corresponds to the ground voltage and the high voltage is close to supply voltage VDD. However, in practice, the high voltage will inevitably be smaller than voltage VDD and moreover tends to decrease along time. This is why a periodic refreshment of the memory cells is further provided. Before each read operation, a bit line precharge operation is performed, that is, a given voltage, currently VDD/2, is applied to each bit line and is stored on the capacitor of this line. During an actual read operation, such as illustrated in FIG. 2, at a time t0, a memory cell is addressed and voltage VDD/2 initially existing on the bit line rises if the involved memory cell has stored a xe2x80x9c1xe2x80x9d (high voltage) and falls if the involved memory cell has stored a xe2x80x9c0xe2x80x9d (low voltage), and differential amplifier 10 measures the difference between this raised voltage or this lowered voltage and voltage VDD/2. However, due to the dissymetry of the operations of charge of a xe2x80x9c1xe2x80x9d and of a xe2x80x9c0xe2x80x9d, the difference between the two inputs of the operational amplifier will be smaller in the case where a xe2x80x9c1xe2x80x9d has been stored than in the case where a xe2x80x9c0xe2x80x9d has been stored. This difference will for example be, as indicated in FIG. 2, on the order of 100 millivolts for the storage of a xe2x80x9c1xe2x80x9d and on the order of 150 millivolts for the storage of a xe2x80x9c0xe2x80x9d. To solve this problem, the voltage received by the input of amplifier 10, which is not connected to the read memory cell, is generally modified to be made to fall to a value VREF smaller than VDD/2, so that, as illustrated in FIG. 2, the difference between voltage VREF and a high read voltage is substantially the same as the difference between voltage VREF and a low read voltage.
FIG. 3 schematically shows a conventional DRAM 12, similar to memory 2 of FIG. 1, each bit line of which is further connected to a voltage adjustment cell 14 (REF). Each of cells 14 is activated to bring the line to which it is connected to previously-defined value VREF at the beginning of a read phase of an adjacent line. Cells 14 are connected by activation lines 16 (RL1, RL2) to the row address decoder (not shown). The structure of voltage adjustment cells 14, which is known, will not be detailed herein.
Further, conventional DRAMs such as those described in FIGS. 1 and 3 come up against other problems. Indeed, the bit lines are generally relatively long and very close to one another. Thus, when two bit lines are simultaneously read, the voltage present on the first bit line can have an influence upon the voltage of the second bit line and disturb its reading. A solution to this problem consists of having each pair of bit lines cross once or several times, as schematically shown in FIG. 4A.
FIG. 4A shows two bit line pairs (BL1, BL2 and BL3, BL4) of a DRAM 18 with 256 rows. Each bit line is connected to 128 alternately arranged memory cells 4 (MC). Further, due to the bit line crossings, the rows of memory 18 are arranged in four sectors of 64 rows each, respectively corresponding to rows 1 to 64, 65 to 128, 129 to 192, and 193 to 256.
In the first sector, each odd row includes two adjacent memory cells respectively connected to bit lines BL1 and BL3 and each even row includes two adjacent memory cells respectively connected to bit lines BL2 and BL4. Bit lines BL1 and BL2 cross between rows 64 and 65 so that, in the second sector, the memory cells of the odd rows are respectively connected to bit lines BL2, BL3, and the memory cells of the even rows are respectively connected to bit lines BL1, BL4. Similarly, lines BL3 and BL4 cross between rows 128 and 129. Finally, lines BL1 and BL2 cross between rows 192 and 193. Each row can be activated by a word line WL1 to WL256.
Some memory cells 4 may be defective. To replace the defective cells, spare cells arranged in rows and columns are generally provided. When a defective cells is found, the row or column where this cell is present is xe2x80x9creplacedxe2x80x9d with a spare row or column. This is done by modifying the address decoder so that it addresses, instead of the defective row or column, a spare row or column. When several cells in a same row are defective, the row of these cells is xe2x80x9creplacedxe2x80x9d, which eliminates several defects at once.
FIG. 4B schematically shows rows of spare cells SC intended for replacing a defective row of memory 18. Bit lines BL1 to BL4 correspond to the end of the bit lines of FIG. 4A. Since there are four types of memory cell rows in memory 18, it is necessary to provide four spare rows to replace any row in the memory. When a row of memory 18 is deflective, the type of row involved is first determined. Then, a predetermined spare row corresponding to the type of the row to be replaced is associated therewith. Thus, for example, the odd rows of sector 1 and the even rows of sector 3 have the same configuration as the first spare row illustrated in FIG. 4B and will be replaced by it. Then, the address decoder will definitively associate the address of the defective row with that of the spare row. Each spare row is activated by an activation line, SELi, which will be activated upon addressing of the row.
When the number of errors desired to be corrected increases, the number of spare rows becomes high (all the more as four types of spare rows must be provided) and this creates many problems. Thus, the presence of many spare rows, connected to the bit lines, imposes a significant lengthening thereof, which reduces the voltage variation associated with the reading from a cell of a bit line. Also, when the number of spare rows is increased, the risks for a cell in a spare row to be itself defective is increased for statistical reasons, and the provision of spare cells replacing possible defective spare cells risks making the system complicated and difficult to manage. The spare rows further increase the total surface area occupied by the memory and the cost thereof. Further, the step of replacing a row containing a defective cell with a spare row is complex, since it requires precisely identifying the type of the row to replace it with an appropriate spare row taken from among all the available spare rows.
An object of the present invention is to provide, in a memory circuit, a spare memory cell row structure having a simpler and more efficient implementation.
Another object of the present invention is to provide such a circuit that occupies a reduced surface area as compared to conventional circuits with spare cells.
To achieve these objects, as well as others, the present invention provides a dynamic memory circuit including memory cells arranged in an array of rows and columns, each row being capable of being activated by a word line and each column being formed of cells connected to a first and to a second bit line, which includes at least one spare row formed of static memory cells, adapted to being activated to replace a memory cell row, each spare cell being connected to the first and second bit lines of a column of the circuit.
According to an embodiment of the present invention, the memory cell row replaced by the spare row is not addressed upon addressing of the spare row.
According to an embodiment of the present invention, the memory cell row replaced by the spare row is addressed upon addressing of the spare row.
According to an embodiment of the present invention, the bit lines cross at least once.
According to an embodiment of the present invention, the memory circuit further includes a sense amplifier on each memory column, the inputs of the amplifier being respectively connected to the first and second bit lines.
According to an embodiment of the present invention, the memory circuit further includes rows of voltage adjustment cells arranged either between the memory, cells of the memory and the spare cells or between the spare cells and the sense amplifiers.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.